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FPGA Design Flow Automation using Agentic AI

1 hour session (All Time Zones)
Presenter: Dr Rahul Dubey

Doulos Member Technical Staff

Asia and Europe

Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)


Americas

Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)


Webinar Overview:

This webinar will discuss the use of Agentic AI to automate your FPGA design flow using AMD Ross Agentic AI assistant for Vivado Design Suite.

Topics include:

  • Use of an autonomous car analogy to understand an automated design flow

  • Working of Retrieval-Augmented Generation (RAG) based knowledge base to assist Agentic AI

  • Closed loop mechanism to resolve errors in the design flow

  • Use of a Model Context Protocol (MCP) server to interface with a large language model, knowledge base, and Vivado Design Suite

  • Trade-offs in using cloud-based frontier models or on-perm based local models

  • Creating a deterministic workflow using skills to avoid model hallucinations

  • Pre-built AI agent skills and an example of creating your own custom skill

  • Examples on the use of Agentic AI for block-based design creation, RTL linting, timing closure and insertion of integrated logic analyzer (ILA) probes for design debugging

Attendance is free of charge.


Dr Rahul Dubey

Dr Rahul Dubey - Doulos Member Technical Staff - will present this webinar, with interactive Q&A for attendees throughout.


Attendance is free of charge

If you have any queries, please contact webinars@doulos.com


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