Simulating Clock Circuits

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Simulating Clock Circuits

Sometimes users find that they need to run a simulation of VHDL code containing behavioral models of clocking circuits. These include Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs).

If you do this, it is important to make sure that the time resolution of your simulator is set correctly. Many simulators default to 1 ns time resolution. Any value that is less than 1 ns will be reduced to 0. This is a problem in certain models. For instance Xilinx DLLs contain a delay-line made up of a sequence of either 25ps or 50ps delay steps - which is smaller than 1 ns, so a behavioral model of such a DLL will not work unless the time resolution is set.

If you run a simulation launched from the FPGA vendor's development environment, then you should find the time resolution is set appropriately - probably to picoseconds. However if you run simulation stand-alone in your simulator, you must remember to do this yourself.

Here are some examples of setting time resolution in a range of different simulators.

Mentor Modelsim

From the command line, or in a Tcl script:

  vsim -t ps file.vhd

From the GUI:

Select menu Simulate > Start Simulation...
Use the drop down box labelled Resolution to select a different resolution
Highlight the testbench to simulate
Click OK

To change the default resolution:

Find the installation directory of Modelsim
In that directory, make the file modelsim.ini writeable

Edit modelsim.ini and change the following lines to your required default resolution

; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ns

Save modelsim.ini, and make it read-only

Aldec Active-HDL

From the command line, or in a Tcl script:

  asim -t ps file.vhd

From the GUI:

Select menu Design > Settings...
Highlight the category Simulation
Use the drop down box labelled Simulator Resolution to select the required resolution
Click OK

To change the default resolution:

Find the installation directory of Active-HDL
Edit the file bin\vsimsa.cfg

Change the resolution by editing the following lines:

; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
;0 means resolution is default

Resolution = 0

Save vsimsa.cfg

Cadence ncsim

Cadence ncsim defaults to a resolution of femtoseconds, so you normally don't need to set the resolution explicitly. If you did, you could use the irun script as follows:

  irun -vhdl_time_precision '1 ps' ...

In Verilog, just use the `timescale directive as normal.

Synopsys VCS-MX

There are options for setting both the simulation timebase and the time resolution

  vcs -time 1 ns -time_res 1 ns ...

Verilog

Most simulators provide a means of overriding the Verilog timescale from the command line. However normally `timescale directives are added to source code.

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