Synthesizing a Black Box

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Synthesizing a Black Box

First some background: what is a Black Box? In synthesis, it is part of your design which is empty (contains no code). It might be an empty Verilog module instance, or an empty VHDL component instance.

A missing piece of code occurs when you use a pre-written piece of design, typically a piece of IP. All the main FPGA vendors provide a way of generating a design as a kind of macro - a piece of design that can be put into your final chip during place and route (or fitting). Tools like this include

Altera MegaWizard
Actel SmartGen
Lattice IPExpress
Xilinx CoreGen

(By the way, you'll get to try one of these tools if you come on Comprehensive VHDL)

Let's look at what happens in a bit more detail.

Running an IP Generation Tool

Running an IP Generation Tool (perhaps one of the four mentioned above) gives you a friendly GUI to type in your requirements for your piece of IP. Once the tool has finished, it will generate code. Typically you will get:

A behavioral simulation model not synthesizable!
An instantiation template to cut and paste into your code
A so called "hard macro", that is the design in a format suitable for place and route; or a VHDL or Verilog file containing an instance of a known hardware component.

Synthesis of a piece of IP

The IP may be created as a hard macro, in a format understood by the place and route tool. This means that for synthesis, there is no implementation of the component - it is empty, a black box. This normally results in a warning during synthesis, perhaps something like

WARNING:Xst:2211 - "C:/users/training/vhdlfpga/ex09/source/ram1k8_xilinx.vhd"
         line 28: Instantiating black box module .

Note that some tools may even generate an error at this point.

You can normally disable the warning by adding an attribute or meta-comment to your code to tell the synthesis tool that the instance is actually a black-box

Place and Route

At place and route, there really must be some matching implementation, or the component instance name must be built-in to the place and route tool. If there is no matching implementation and the name is not a built-in name, then place and route will fail.

The format of a hard macro is vendor specific. Most tools support a number of formats:

Actel: .edif, .edf, .adl
Altera: .vgm
Lattice: .edif, .ngo
Xilinx: .ngc, .edif

If place and route does fail, you will get a message similar to this:

ERROR:NgdBuild:604 - logical block 'ram1k8cgen_inst' with type 'ram1k8cgen'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, or the misspelling of a type name. Symbol 'ram1k8cgen' is not
   supported in target 'spartan3e'.

A simple solution is to copy the file into the appropriate location, typically inside a project directory. In some tools you can simply add the file to the project.

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