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Sequential Processes
Design for Debug
Creating a Reference Model
Deferred Constants
Encapsulation in VHDL
Avoid Synthesizing Unwanted Latches
Re-using Code Snippets
Re-usable Functions
Synthesizing "+" : Part One
Synthesizing "+" : Part Two
Clock Generation
Magic Numbers
Beware those 'if' statements
Using LUT Architectures in FPGAs
Unrolling Loops
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