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Doulos extends SystemVerilog methodology training with Cadence

June 2007|Press release

Doulos extends SystemVerilog methodology training with Cadence

Doulos, the independent training specialist, has announced the availability of a full scope training class for logic design groups focusing on the application of SystemVerilog to module based verification using the Cadence® Incisive® Plan-to-Closure Methodology.

The ground breaking course development resulted from direct co-operation between Doulos and Cadence within the Cadence Verification Alliance. Doulos is releasing this training course as part of its SystemVerilog Out of the Box™ initiative announced at DAC 2007 in San Diego.

The 4 day training entitled SystemVerilog using Design Team Verification Methodology is targeted at logic design teams who are committed to improve their verification skills and project productivity.

The course will be presented on scheduled dates through the summer and fall in both the USA and Europe and is available on a global basis for in-house team based training as part of the full scope Doulos Modular SystemVerilog program.

Currently the following dates and locations are scheduled:

Austin TX: September 24 to 27
San Jose CA: August 21 to 24
Munich Germany: October 15 to 18

More details: email or call 1-888-GO-DOULOS

About Doulos

Since 1991 Doulos has set the industry standard for high quality language and methodology training in SystemC, SystemVerilog, e, PSL, VHDL, Verilog, Perl and Tcl/Tk. A completely independent company, Doulos in-house expertise and world leading know-how has contributed to the success of more than 600 companies across 30 countries.

Marketing contact:
Rachael Mundy
Doulos Marketing Manager
info@doulos.com

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Doulos extends SystemVerilog methodology training with Cadence

Doulos extends SystemVerilog methodology training with Cadence

About Doulos

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Doulos extends SystemVerilog methodology training with Cadence

Doulos extends SystemVerilog methodology training with Cadence

About Doulos

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