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Arm Cortex-M7 System Design

Standard Level - Live Instructor-Led Training

5 sessions (Live Online) 6 hours per session

This course is crafted for those who are designing hardware based around the Arm® Cortex®-M7 core. Including an introduction to the Arm product range and supporting IP, the course covers the Armv7-M instruction set and exception handling, Cortex-M7 implementation, memory protection and AMBA on-chip bus architecture. The Cortex-M7 debug architecture is also covered.

Hardware design as well as verification engineers who need to understand the issues involved when designing SoC's around the ARM Cortex-M7 core.

  • Some knowledge of embedded systems
  • Familiarity with digital logic and hardware/ASIC design issues
  • A basic awareness of ARM is useful but not essential

This class uses training materials developed by Arm and is complemented by Doulos' own lecture and laboratory material. This offers the students a well rounded and practical view of the topics covering both the Processor's features along with how to program it.

Arm Cortex-M7 Overview

 

  • Block diagram
  • Micro-architectural features
  • Instruction set
  • Memory interfaces
  • System buses
  • TCM/Caches
  • Memory protection
  • Pipeline features
  • Lock-step operation

 

Armv7-M Programmers' Model

 

  • Introduction
  • Data Types
  • Core Registers
  • Modes, privilege and stacks
  • Exceptions
  • Instruction Set Overview
  • Programming standards

 

Armv7-M Assembly Programming

 

  • Introduction
  • Data Processing Instructions
  • Load/Store Instructions
  • Flow Control
  • Miscellaneous

 

Cortex-M7 Processor Core

 

  • Processor Pipeline
  • Execution Pipelines
  • Prefetch Unit
  • Memory-mapped Registers

 

Introduction to AMBA Protocols

 

  • AXI Protocol
  • AHB Protocol
  • APB Protocol

 

Cortex-M7 Level 1 Sub-Systems

 

  • Caches
  • Cache Fundamentals
  • Cortex-M7 L1 Cache Sub-system
  • Tightly Coupled Memory (TCM)
  • System Considerations

 

SysTick Timer

 

  • Overview
  • Calibration Examples
  • System Control

 

Armv7-M Memory Model

 

  • Introduction
  • Memory Address Space
  • Memory Types and Attributes
  • Alignment and Endianness
  • Barriers

 

Armv7-M Memory Protection

 

  • Memory Protection Overview
  • Memory Regions
  • Region Attribute Control
  • Region Overlapping
  • Sub-region Support
  • Setting up the MPU

 

Armv7-M Exception Handling

 

  • Introduction
  • Exception Model
  • Exception Entry and Exit Behavior
  • Prioritization and Control
  • Interrupt Sensitivity
  • Writing the Vector Table and Interrupt Handlers
  • Internal Exceptions and RTOS Support
  • Fault Exceptions

 

Armv7-M Debug

 

  • Introduction to Debug
  • Debug
  • Events and Reset
  • Flash Patch and Breakpoint Unit (FPB)
  • Data Watchpoint and Trace Unit (DWT)
  • Instrumentation Trace Macrocell (ITM)
  • Embedded Trace Macrocell (ETM)
  • Trace Port Interface Unit (TPIU), Trace Packets, Timestamping & Trace Bandwidth

 

Appendix

 

  • Armv7-M Extensions
  • Extensions Overview
  • DSP Extension
  • Floating-point Extension

 

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