AMD - Design Closure Techniques

Standard Level - Live Instructor-Led Training

2 days (In-Person) 8 hours per day or
3 sessions (Live Online) 6 hours per session

I am interested in a combination of training (contact Doulos to discuss your options) »

Course Description

Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results.

The emphasis of this course is on:

Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
Using recommended coding techniques
Creating a test bench and running simulation for functional verification
Applying initial design checks and reviewing timing summary and methodology reports for a design
Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
Performing quality of results (QoR) assessments at different stages to improve the QoR score
Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
Reviewing the importance of power closure and device selection
Estimating power consumption by using the Vivado™ Design Suite Power Report utility and performing power optimization on a design
Identifying Versal™ adaptive SoC power and thermal solutions
Utilizing architecture features to improve a design's power consumption

Who should attend?

Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure

Prerequisites

Basic knowledge of FPGA and SoC architecture and HDL coding techniques
Basic knowledge of the Vivado™ Design Suite

Software Tools

Vivado™ Design Suite

Skills Gained

After completing this training, you will have the necessary skills to:

Describe what is design closure is as well as its three pillars
Create a test bench and run simulation for functional verification
Resolve setup and hold violations by reducing logic delay and net delay
Improve clock skew and clock uncertainty
Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
Perform QoR assessment at different stages and improve the QoR score
Implement Intelligent Design Runs (IDR)
Apply the power closure flow for better time to market
Estimate power consumption by using the AMD Power Estimator (XPE)
Describe Versal adaptive SoC power and thermal solutions
Perform power optimization on a design

Course Outline

Introduction

Introduction to Design Closure
Defines what design closure is and identifies the three pillars of design closure. {Lecture}

Functional Closure

HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design. {Lecture}
Creating a Test Bench
Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed. {Lecture}
Behavioral Simulation
Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}
Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware. {Lecture, Lab}

Timing Closure

Introduction to Clocking and Static Timing Analysis (STA)
Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}
Introduction to UltraFast Design Methodology Timing Closure
Provides an overview of the various stages of the UltraFast Design Methodology for timing closure. {Lecture}
Baselining
Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab}
Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}
Reducing Logic Delay
Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}
Reducing Net Delay
Reviews different techniques to reduce congestion and net delay. {Lecture, Lab}
Improving Clock Skew
Describes how to apply various techniques to improve clock skew. {Lecture}
Improving Clock Uncertainty
Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}
Clock Domain Crossing (CDC) and Synchronization Circuits
Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab}
QoR Reports Overview
Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab}
Intelligent Design Runs (IDR)
Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

Power Closure

Understanding Design Power for Better Time to Market
Outlines the types of design power, describes the power closure flow, and identifies methods for bringing down the power of a device. {Lecture, Lab}
AMD Power Estimator Spreadsheet
Demonstrates how to estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
Versal adaptive SoC: Power and Thermal Solutions
Discusses the power domains in the Versal adaptive SoC as well as power optimization and analysis techniques. Thermal design challenges are also covered. {Lecture}
Design Power Constraints
Describes what design power constraints are and how to use the Power Constraints Advisor tool. Power rail constraints are also covered. {Lecture}
Power Management Techniques
Identifies techniques used for low power design. {Lecture}
Power Analysis and Optimization Using the Vivado Design Suite
Covers how to use report power commands to estimate power consumption. {Lecture, Lab}

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