AMD - Designing with the Versal Adaptive SoC: Network on Chip

Standard Level - Live Instructor-Led Training

1 day (In-Person) 8 hours per day or
2 sessions (Live Online) 4 hours per session

I am interested in a combination of training (contact Doulos to discuss your options) »

Course Description

This course introduces the Versal™ Adaptive SoC network on chip (NoC) to users familiar with AMD devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on:

Enumerating the major components comprising the NoC architecture in the Versal Adaptive SoC
Implementing a basic design using the NoC
Configuring the NoC for efficient data movement

Who should attend?

Hardware developers and system architects whether migrating from existing AMD devices or starting out with the Versal Adaptive SoC devices

Prerequisites

Any AMD device architecture class
Familiarity with the Vivado™ Design Suite

Software Tools

Vivado Design Suite

Hardware Tools

Architecture: AMD Versal Adaptive SoCs

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Identify the major network on chip components in the Versal Adaptive SoC
Include the necessary components to access the NoC from the PL
Configure connection QoS for efficient data movement

Course Outline

Architecture Overview for Existing AMD Users
Introduces to students that already have familiarity with AMD architectures to the new and updated features found in the Versal Adaptive SoC devices. {Lecture}
Versal Adaptive SoCs Compared to Zynq UltraScale+ Devices
The Versal Adaptive SoC has a number of similarities to the Zynq™ UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. {Lecture}
NoC Introduction and Concepts
Reviews the basic vocabulary and high level operations of the NoC. {Lecture, Lab}
NoC Architecture
Provides the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic {Lecture}
Design Tool Flow Overview
Designers come to the Versal Adaptive SoC devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the AMD toolbox. {Lecture}
NoC DDR Memory Controller
The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}
NoC Performance Tuning
Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}
System Design Migration
Describes how different users will leverage tools and processes to migrate their designs to the Versal Adaptive SoC devices. {Lecture}

Full details below