AMD - DSP Design Using System Generator

Standard Level - Live Instructor-Led Training

2 days (In-Person) 8 hours per day or
3 sessions (Live Online) 6 hours per session

I am interested in a combination of training (contact Doulos to discuss your options) »

Course Description

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost Digital Signal Processing designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using AMD FPGA capabilities.

Who Should Attend?

System engineers, system designers, logic designers and experienced hardware engineers interested in DSP design training who are implementing DSP algorithms using the MathWorks MATLAB^® and Simulink^® software and want to use AMD System Generator for DSP design

Prerequisites

Experience with the MATLAB and Simulink software
Basic understanding of sampling theory

Software Tools

Vivado™ Design Suite System Edition
Model Composer
MATLAB with Simulink software

Hardware

Architecture: 7 series and UltraScale™ FPGAs*
Demo board: Kintex™-7 FPGA KC705 board or Kintex UltraScale™ FPGA KCU105 board and Zynq™ UltraScale+™ MPSoC ZCU104 board*

*Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The ZCU104 board is required for the "AXI4-Lite Interface Synthesis" lab.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the System Generator design flow for implementing DSP functions
Identify AMD FPGA capabilities and implement a design from algorithm concept to hardware simulation
List various low-level and high-level functional blocks available in System Generator
Run hardware co-simulation
Identify the high-level blocks available for FIR and FFT designs
Implement multi-rate systems in System Generator
Integrate System Generator models into the Vivado IDE
Design a processor-controllable interface using System Generator for DSP
Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Introduction to System Generator
Simulink Software Basics
Lab 1: Using the Simulink Software
Basic AMD Design Capture
Demo: System Generator Gateway Blocks
Lab 2: Getting Started with AMD System Generator
Signal Routing
Lab 3: Signal Routing
Implementing System Control
Lab 4: Implementing System Control
Multi-Rate Systems
Lab 5: Designing a MAC-based FIR
Filter Design
Lab 6: Designing a FIR Filter Using the FIR Compiler Block
System Generator, Vivado Design Suite, and Vivado HLS Integration
Lab 7: System Generator and Vivado IDE Integration
DSP Platforms
Lab 8: System Generator and Vivado HLS Tool Integration
Lab 9: AXI4-Lite Interface Synthesis
Introduction to Model Composer
Demo: Introduction to Model Composer
[OPTIONAL]: Importing C/C++ Code to Model Composer
[OPTIONAL]: Automatic Code Generation Using Model Composer
[OPTIONAL]: Lab 10: Model Composer and Vivado IDE Integration

Lab Descriptions

Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
Lab 2: Getting Started with AMD System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting an AMD evaluation board.
Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.
Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using an AMD evaluation board.
Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using an AMD evaluation board.
Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.
Lab 8: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.
Lab 9: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq UltraScale+ MPSoC processor system.
Lab 10: Model Composer and Vivado IDE Integration - Embed a Model Composer model into the Vivado IDE.

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