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What Can Formal Do for Me?

1 hour session (All Time Zones)
Presenter: Doug Smith

Design & Verification Expert

Asia and Europe

Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)

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Americas

Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

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Webinar Overview:

We know formal can prove things, but where do we apply it? Did you know you can use formal to generate simulation testbenches for covering coverage holes or have it visualize your design without writing a single line of testbench code?

Formal can be used for identifying metastability, X propagation, fault propagation and detection, equivalence, and so much more.

In this webinar, we'll have a look at the many ways formal helps out your design verification process, including the use of complexity analysis and bounded reachability analysis, overconstraining the design, setting cut points, and creating abstractions.

Some examples will be demonstrated using the Jasper Formal Verification Platform by Cadence.

This FREE webinar consists of a one-hour presentation delivered by Doug Smith - Design & Verification Expert, and interactive Q&A with Doulos experts available to attendees throughout.

If you have any queries, please contact webinars@doulos.com

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