Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or IC design at the register-transfer level (RTL) and for block-level verification.

Verification engineers who want to use SystemVerilog for module-based verification (including constrained-random, coverage-driven verification) for the first time.

Verification engineers who plan to go on to class-based verification with UVM in the Doulos Essential UVM course.

The course is divided into four sections:

• Core SystemVerilog lays the foundations for learning the SystemVerilog language for verification.

• SystemVerilog Assertions teaches the principles of assertion-based design and verification and the features of the SVA language.

• SystemVerilog RTL provides comprehensive training in all the areas of the SystemVerilog language used for hardware design.

• Module-based SystemVerilog Verification teaches the verification features of SystemVerilog that can be used in module-based code. It also provides a foundation for class-based verification.

Attendees should have a basic working knowledge of digital hardware design or have attended Essential Digital Design Techniques (or equivalent). No previous SystemVerilog (or Verilog) knowledge is required.

Doulos course materials are renowned for being the most comprehensive and user-friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought-after resources in their own right. Course fees include:

• Fully indexed class notes creating a complete reference manual

• Workbook full of practical examples and solutions to help you apply your knowledge

• Doulos Golden Reference Guide for SystemVerilog

Core SystemVerilog

Introduction

Provides an introduction to SystemVerilog.

What is SystemVerilog? • Language features • Simplified design flow • Resources

Modules

Covers the basic features of SystemVerilog.

Modules and ports • Continuous assignments • Rules and regulations • Concurrency • Hierarchy • Testbenches • Simple processes

Numbers and Formatting

Describes numbers and data types in SystemVerilog, together with its text-formatting features and further module-based features.

Logic values • Vectors • 2- and 4-state types and values • Numbers • Truncation and extension • Signed values • Formatted output • Immediate assertions • Formatting strings with $sformatf • Always blocks • Time units • Ending simulation and final blocks

RTL and Programming Features

Covers the basic RTL and general-purpose programming features of SystemVerilog.

Always blocks • Combinational and sequential logic • Local variables • Static and automatic variables • if, case and loop statements • begin…end, fork…join

Operators and Names

Consolidates knowledge of SystemVerilog's operators and introduces hierarchical names.

Operators and expressions • Part selects and concatenation • Replication • Hierarchical names

Arrays

Provides an introduction to SystemVerilog's array types.

Arrays in SystemVerilog • Packed and unpacked data • Streaming operators • Array querying functions • Array initialization

Tasks and Functions

Describes tasks and functions in SystemVerilog.

Tasks • Static and automatic tasks • Reference arguments • Functions • Void functions

File Organization and Parameters

Covers compiling and compiler directives, and module parameterization.

Text macros and `include • Conditional compilation • let • Parameters and parameter overriding • localparams

Types

Describes SystemVerilog's more complex types.

2- and 4-state types • Strings • Enumerated types • Packages • Structs • Unions • Initial values

SystemVerilog Assertions

The SVA part is presented as a self-paced, blended-learning module in the in-purpose version of this course.

The SVA Language

Covers the basic features of SystemVerilog Assertions.

Properties and assertions • Benefits of assertions • Immediate and concurrent assertions • Implication and $past • Simulation and coverage • Embedded assertions and bind • Satellite code and free variables

Properties, Assertions and Sequences

Shows how to construct simple properties, assertions and sequences.

Implication • Cycle delay (##) • $rose, $fell, $past, $stable, $sampled • Named sequences and properties • Concatenation and repetition of sequences • Sequences and implication

SystemVerilog RTL

Implementing SystemVerilog as Hardware

Provides an introduction to using SystemVerilog to design hardware.

How SystemVerilog models hardware • FPGAs and ICs • Design flow and tools • FPGAs • Synchronous design • Tcl

Synthesizing Combinational Logic

Shows how to design and synthesize combinational logic.

Sensitivity lists and always_comb • if statements • Incomplete assignment and latches • Continuous assignment • unique/priority • for loop synthesis • Synthesizing functions

Arithmetic

Describes arithmetic in SystemVerilog and its synthesis.

Synthesis of arithmetic operators • Expression bit lengths and casting • Signed and unsigned arithmetic • Choice of adders • Resource sharing

Clocks and Flip-flops

Shows how to write SystemVerilog in order to achieve efficient synthesis of clocked logic.

Synthesizing flip-flops • Simulation races • Synchronous and asynchronous resets • Synthesizable always templates • Clock enables • RTL synthesis and pipelining • Implying and avoiding registers

Memories

Describes the modeling and synthesis of memories.

Modeling and synthesizing memories • Instantiating memories • Initializing memories

FSM Synthesis

Shows how to write and synthesize finite state machines (FSMs) using SystemVerilog enumeration types.

State transition diagrams • FSM implementation • Enumeration types • Timing constraints • FSM coding styles • State encoding and unreachable states • Asynchronous inputs

Interfaces

Describes how to use SystemVerilog interfaces.

Interfaces • Interface ports • Ports and parameters to interfaces • Modports • Modport expressions • Synthesizing interfaces • Tasks and functions in interfaces

Other Hardware Topics

Covers other topics related to designing hardware in SystemVerilog.

Synthesizable types • Nets and implicit wires • Modeling tristates • Packages and ports • Type parameters • Generate

Module-based SystemVerilog Verification

The two final lectures will be presented if time allows in the in-purpose version of this course.and the.

Clocking Blocks

Describes how to develop a consistent and reliable timing model for connecting a SystemVerilog testbench to the design under test.

Clocking blocks • Input and output skew • Clocking drives and synchronization • #1step sampling

Randomization

Shows how to use SystemVerilog's randomization features for module-based verification.

Constrained random verification • Random numbers in SystemVerilog • Randomize with inline constraints • Random stability • Generating random stimulus • randcase and randsequence

Coverage

Shows how to collect functional coverage information in the context of a SystemVerilog module.

Covergroups, coverpoints and bins • Options • Transition coverage • Cross coverage • Procedural sampling and custom sample method • Constructor arguments • Multiple covergroup instances

Arrays and Queues

Describes the data types that SystemVerilog introduces for verification.

Dynamic arrays • Queues • Associative arrays

File I/O

Shows how to read and write files using SystemVerilog.

Opening and closing files • Reading and writing formatted data • Handling errors

The Direct Programming Interface

Shows how to interface between SystemVerilog and C using the Direct Programming Interface (DPI).

Importing and exporting tasks and functions • Passing data between C and SystemVerilog • Changing the function/task name • Calling C++ • DPI flow and simulator switches • Pure and context tasks and functions