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Essential UVM

Standard Level - Live Instructor-Led Training

4 days (In-Person) 8 hours per day or
5 days (Live Online) 6 hours per session

SystemVerilog is the dominant language standard for digital design and verification. The Universal Verification Methodology (UVM) is an IEEE standard functional verification methodology for SystemVerilog that is endorsed and supported by all major SystemVerilog simulator vendors.

Essential UVM provides a complete and integrated training program to fulfill the requirements of verification engineers wishing to exploit the potential of class-based verification in general and UVM in particular.

The UVM source code is freely available from Accellera under an open-source Apache license. UVM offers a complete framework for the creation of sophisticated functional verification environments in SystemVerilog and encourages the development and deployment of reusable verification components.

UVM has comprehensive support for constrained random stimulus generation, including structured sequence generation, and for transaction-level modeling. UVM testbenches also support functional coverage collection and assertions. UVM exploits the object-oriented programming (or class-based) features of SystemVerilog. The open structure, extensive automation, and standard transaction-level interfaces of UVM make it suitable for building functional verification environments ranging from simple block-level tests to the most complex coverage-driven testbenches. The UVM register layer provides a standard way to model, access and check the registers in the design under test.

Workshops comprise approximately 50% of class time and are based around carefully designed exercises that reinforce and extend what you have learned. The course duration is 4 days if taught in person and 5 days if taught online (4 days of 6 hours).

Doulos is an independent company, enabling attendees to receive the benefit of objective training while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:

  • Cadence Xcelium®

  • Siemens EDA Questa®

  • Synopsys VCS®

Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.

Verification engineers who wish to deploy complex SystemVerilog verification environments using class-based SystemVerilog and UVM.

Design engineers who wish to make full use of SystemVerilog's class-based verification capabilities for test bench development using UVM.

The course is divided into two distinct sections:

  • Class-based SystemVerilog Verification describes how to write sophisticated constrained random, coverage-driven, object-oriented testbenches. This material leverages Doulos's years of experience in teaching object-oriented verification concepts, making these challenging topics accessible to engineers with a wide variety of backgrounds. This section of the course has been specifically tailored to provide the ideal preparation for learning UVM

  • The UVM section will teach you all of the features of UVM necessary to implement a complete UVM testbench, including:

  • The principles of effective functional verification using UVM

  • The standard structure of UVM components and environments

  • How to use the UVM base class library in constructing your own verification environments

  • How to make good use of UVM features for configuration, stimulus generation, reporting and diagnostics

  • How to build complete, powerful, reusable class-based UVM verification components and environments

  • How to use the UVM register layer

More advanced features of UVM are covered in the Doulos Advanced UVM follow-on course.

Attendees must have either attended the Doulos Comprehensive SystemVerilog course or must have gained a knowledge of module-based SystemVerilog verification.

Doulos course materials are renowned for being the most comprehensive and user-friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought-after resources in their own right. Course fees include:

  • Fully indexed course notes that form a complete reference manual

  • Workbook full of practical examples to help you apply your knowledge

  • Doulos Golden Reference Guide for UVM

Class-based SystemVerilog

Introduction

Introduces SystemVerilog and UVM, and points to further resources.

What is SystemVerilog? • What is UVM? • Resources

Classes for Transactions

Shows how to create and use SystemVerilog classes and objects for verification.

Classes • Objects • Initialization and constructors • Static and constant members and methods • Randomization and inline constraints • Forward typedef • Members of class type, shallow and deep copy

Building a Verification Environment

Shows how to structure a class-based testbench so that it can operate alongside a design under verification.

Linking a class-based testbench to the DUT • Driver (BFM) class • Interfaces and virtual interfaces • Clocking blocks and modports • Structuring a class-based testbench • Parameterized virtual interfaces

Extending Classes for Stimulus

Shows how to use constraints and how to extend classes to generate constrained random stimulus.

Generator template objects • Constraints in classes • Extending classes • Control knobs • Base-class variables and derived-class objects • Virtual methods

TLM and Channels

Describes how to use channels for transaction-level communication between components.

Channels to decouple components • Base class for transaction data • Out-of-block method declarations • Downcasting and $cast • Parameterized classes • Running self-contained components with fork...join

Component Hierarchy

Shows how to use classes and inheritance to build a hierarchy of verification components.

Implementing a component hierarchy using classes • Abstract classes and pure virtual methods • Component base class • local and protected class members • Launching a task with fork...join_none • Extending the Component base class

Monitors and Subscribers

Describes the use of monitors and subscribers in a class-based verification environment.

Passive monitors and unbounded FIFOs • Modports for driver and monitor • Checkers • Coverage in classes • Subscribers

UVM

Introduction to UVM

Discusses the motivation for UVM and gives an overview of its main features.

The UVM standard • Versions of UVM • The UVM class hierarchy • A brief introduction to tests, environments, agents, TLM, phases, factory, sequences and virtual sequences, configuration

Getting Started with UVM

Introduces the UVM library features required for a simple testbench.

Transaction and sequence classes • Sequencer, driver, monitor, agent, env, test classes • Ports • build_phase, connect_phase, run_phase • Starting a sequence • Top-level module • Configuration database

Reporting

Covers the basic report features of UVM.

Severity, id, and verbosity • Report macros • Setting actions and overriding severity • uvm_top and "uvm_test_top" • Print topology • Scope of report settings • Reports outside components

Transaction-Level Modeling

Describes ports, exports, analysis ports, subscribers and scoreboards.

Ports, exports, and imps • Push versus pull interfaces • The sequencer-driver connection • Analysis ports • Copying and comparing transactions • Subscribers: reference models and scoreboards • Debugging connections

Sequences

Provides a deeper understanding of sequences, sequence macros, and the sequence-driver interaction.

uvm_sequence class • Starting sequences • p_sequencer • `uvm_do • Sequence-driver interaction • Constraining transactions and control knobs • Nested sequences

The Factory & Configuration Database

Shows how to use the factory and the configuration database.

The factory • Factory overrides • The configuration database • Multiple configuration entries • Agent configuration • Sequence configuration • Debugging the factory and configuration

Objections

Describes the objection mechanism and how to raise and drop objections.

Raising and dropping objections • Objections within sequences • pre_start and post_start • Test completion • Tracing objections

Methods of uvm_object

Shows how to go beyond field macros when customizing the behavior of UVM objects.

Field macros • Printing • Overriding the methods

Virtual Sequences

Shows how to coordinate several agents using virtual sequences, with or without a virtual sequencer.

Virtual sequence • Virtual sequencer • p_sequencer or m_parent • Virtual sequence without a sequencer

Responses

Shows how to send responses from the driver.

Sending information upstream • Request versus response versus monitor • The driver response

Register Layer

Describes the UVM register layer and how to implement a register model for a design under test.

Introduction and motivation • Frontdoor versus backdoor access • Registers and fields • Integration into the verification environment • Adapters • Register sequences and tests

UVM 2020

Describes the changes from UVM 1.2 to UVM 2020: compatibility issues and new features.

Upgrading • Top-level module • Deprecated classes • Policy classes • `uvm_do • Factory and configuration • Register layer

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