Advanced UVM

Advanced Level - Live Instructor-Led Training

4 days (In-Person) 8 hours per day or
5 days (Live Online) 6 hours per session

The Universal Verification Methodology (UVM) is an IEEE standard functional verification methodology for SystemVerilog that is endorsed and supported by all major SystemVerilog simulator vendors.

The Doulos Advanced UVM course teaches advanced and expert UVM verification techniques. Engineers taking this course will learn advanced UVM techniques enabling them to create more powerful test environments and more thorough tests, more easily and more quickly.

Workshops comprise approximately 50% of class time and are based around carefully designed exercises that reinforce and extend what you have learned. The course duration is 4 days if taught in person and 5 days if taught online (4 days of 6 hours).

Doulos is an independent company, enabling attendees to receive the benefit of objective training while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:

Cadence Xcelium®
Siemens EDA Questa®
Synopsys VCS®

Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.

Who should attend?

Engineers taking this course will learn advanced UVM techniques enabling them to create more powerful test environments and more thorough tests, more easily and more quickly.

What will you learn?

The advanced features of UVM such as:

Advanced sequences and sequencers
Layered agents
Advanced register layer, register coverage and memories
Callbacks, events and barriers
Advanced reporting
Run-time phasing
Moving to UVM 2020

Pre-requisites

Attendees must either have attended the Doulos Essential UVM course (or the now retired Doulos UVM Adopter Class) or have gained a detailed knowledge of how to build a UVM verification environment. Specifically, knowledge of the following aspects of UVM is assumed:

testbench structure: classes/components, phases, factory – how to create components, how components communicate
ports and analysis ports
stimulus generation: transactions, sequences, sequencers
config database
reporting
overview of register layer

Course Materials

Doulos course materials are renowned for being the most comprehensive and user-friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought-after resources in their own right. Course fees include:

Fully indexed course notes that form a complete reference manual
Workbook full of practical examples to help you apply your knowledge
Doulos Golden Reference Guide for UVM

Structure and Content

Getting Started with UVM (Refresher)

Revises the UVM features required for a simple testbench in order to ensure a common starting point for the rest of the course.

Transaction and sequence classes • Sequencer, driver, monitor, agent, env, test classes • Ports • build_phase, connect_phase, run_phase • Starting a sequence • Top-level module • Configuration database

More on uvm_object

Covers further uvm_object methods and macros.

Configuration class • Field automation macros • Automatic configuration • Field macros and do_compare • Policy classes • Packing and unpacking • Transaction recording

Advanced Sequence Topics

Describes the advanced features of sequences.

Sequence-driver interaction • Sequence callbacks • Transaction IDs • Pipelined transactions • Response handler • Communicating between sequences • Non-blocking try_next_item

Events and Barriers

Explores the more ad hoc synchronization features of UVM.

uvm_event • Event pools • uvm_barrier

Advanced Sequencer Topics

Describes the advanced features of sequencers.

Push driver/sequencer • Sequence priority and arbitration • Grabbing sequencers from virtual sequences

More on the Register Layer

Covers further features of the UVM register layer, such as mirroring, built-in test sequences and register prediction.

Mirroring and updating • Built-in test sequences • Frontdoor sequences • Register predictor • Backdoor access • Register model hierarchy

Advanced Reporting

Describes advanced report processing.

Sending reports to files • Max quit count • Report context • Report catcher • Report server

Callbacks

Shows how to use the general-purpose UVM callback mechanism.

Callback base class • Inserting callbacks into a component • Implementing specific callbacks

Layering Sequences and Agents

Describes how to layer sequences and agents.

Layering sequences • Layering sequencers • Layering agents • Starting layers from a virtual sequence • Layering monitors

Parameters and Hierarchy

Shows how to use parameterized interfaces and how to navigate the component hierarchy.

Parameterized interfaces • Component hierarchy introspection • Finding components by name

Responses using Analysis Ports

Shows how to use the monitor to pass responses back to the sequencer, and how to use the uvm_tlm_analysis_fifo.

Sequencer and driver analysis ports • Passing response transactions from the monitor • uvm_tlm_analysis_fifo

Simulation Events and Control

Describes ways of controlling the flow and ending of simulation.

Event callbacks • Drain time • Extending a phase • Objection propagation • Heartbeat • Command line processor

Additional Register Topics

Describes the advanced features of the UVM register layer.

Memory

Describes memory handling within the UVM register layer.

Memory access • Setting up a memory within the address map • Using the memory allocation manager • Memory sequence

Run-Time Phasing

Provides an understanding of UVM run-time phasing.

Motivation • The concepts and jargon of phases • Phase synchronization • Domains • User-defined phases

More on Run-Time Phasing

Provides a further understanding of UVM run-time phasing.

Schedules • Domains: set_domain and define_domain • Phase awareness • Phase jumping • VIP integration and recommendations

UVM 2020

Describes the changes from UVM 1.2 to UVM 2020: compatibility issues and new features.

Upgrading • Top-level module • Deprecated classes • Policy classes • `uvm_do • Factory and configuration • Register layer

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