Global training solutions for engineers creating the world's electronics
Menu

SystemVerilog for Verification

Standard Level - Live Instructor-Led Training

4 days (In-Person) 8 hours per day or
5 days (Live Online) 6 hours per session

SystemVerilog is the dominant language standard for digital design and verification. SystemVerilog for Verification provides a complete and integrated training program to fulfill the requirements of verification engineers wishing to use SystemVerilog for module-based verification including constrained-random, coverage-driven verification. It also gives the prerequisite knowledge for those wishing to go on to learn class-based, object-oriented SystemVerilog via the Doulos Essential UVM course.

Workshops comprise approximately 50% of class time and are based around carefully designed exercises that reinforce and extend what you have learned. The course duration is 4 days if taught in-person and 5 days if taught online (5 days of 6 hours).

Doulos is an independent company, enabling attendees to receive the benefit of objective training while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:

  • Cadence Xcelium®

  • Siemens EDA Questa®

  • Synopsys VCS® 

Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.

Verification engineers who want to use SystemVerilog for module-based verification (including constrained random, coverage-driven verification) for the first time.

Verification engineers who plan to go on to class-based verification with UVM such as the Doulos Essential UVM course.

The course is divided into three sections:

  • Core SystemVerilog lays the foundations for learning the SystemVerilog language for verification. It also includes the basics of SystemVerilog for Design, because verification engineers do need some understanding of the designs they are verifying.

  • SystemVerilog Assertions teaches the principles of assertion-based design and verification and the features of the SVA language.

  • Module-based SystemVerilog Verification teaches the verification features of SystemVerilog that can be used in module-based code.

Attendees should have a basic working knowledge of digital hardware design or have attended the Doulos Essential Digital Design Techniques course (or equivalent). No previous SystemVerilog (or Verilog) knowledge is required.

Some basic understanding of verification methodologies such as covered by the Doulos Essential Verification Methodology course would be beneficial but not essential.

Doulos course materials are renowned for being the most comprehensive and user-friendly available. Their style, content and coverage are unique in the HDL training world and have made them sought-after resources in their own right. Course fees include:

  • Fully indexed course notes that form a complete reference manual

  • Workbook full of practical examples to help you apply your knowledge

  • Doulos Golden Reference Guide for SystemVerilog

Core SystemVerilog

Introduction

Provides an introduction to SystemVerilog.

What is SystemVerilog? • Language features • Simplified design flow • Resources

Modules

Covers the basic features of SystemVerilog.

Modules and ports • Continuous assignments • Rules and regulations • Concurrency • Hierarchy • Testbenches • Simple processes

Numbers and Formatting

Describes numbers and data types in SystemVerilog, together with its text-formatting features and further module-based features.

Logic values • Vectors • 2- and 4-state types and values • Numbers • Truncation and extension • Signed values • Formatted output • Immediate assertions • Formatting strings with $sformatf • Always blocks • Time units • Ending simulation and final blocks

RTL and Programming Features

Covers the basic RTL and general-purpose programming features of SystemVerilog.

Always blocks • Combinational and sequential logic • Local variables • Static and automatic variables • if, case and loop statements • begin…end, fork…join

Operators and Names

Consolidates knowledge of SystemVerilog's operators and introduces hierarchical names.

Operators and expressions • Part selects and concatenation • Replication • Hierarchical names

Arrays

Provides an introduction to SystemVerilog's array types.

Arrays in SystemVerilog • Packed and unpacked data • Streaming operators • Array querying functions • Array initialization

Tasks and Functions

Describes tasks and functions in SystemVerilog.

Tasks • Static and automatic tasks • Reference arguments • Functions • Void functions

File Organization and Parameters

Covers compiling and compiler directives, and module parameterization.

Text macros and `include • Conditional compilation • let • Parameters and parameter overriding • localparams

Types

Describes SystemVerilog's more complex types.

2- and 4-state types • Strings • Enumerated types • Packages • Structs • Unions • Initial values

SystemVerilog Assertions

The SVA Language

Covers the basic features of SystemVerilog Assertions.

Properties and assertions • Benefits of assertions • Immediate and concurrent assertions • Implication and $past • Simulation and coverage • Embedded assertions and bind • Satellite code and free variables

Properties, Assertions and Sequences

Shows how to construct simple properties, assertions and sequences.

Implication • Cycle delay (##) • $rose, $fell, $past, $stable, $sampled • Named sequences and properties • Concatenation and repetition of sequences • Sequences and implication

Module-based SystemVerilog Verification

Clocking Blocks

Describes how to develop a consistent and reliable timing model for connecting a SystemVerilog testbench to the design under test.

Clocking blocks • Input and output skew • Clocking drives and synchronization • #1step sampling

Randomization

Shows how to use SystemVerilog's randomization features for module-based verification.

Constrained random verification • Random numbers in SystemVerilog • Randomize with inline constraints • Random stability • Generating random stimulus • randcase and randsequence

Coverage

Shows how to collect functional coverage information in the context of a SystemVerilog module.

Covergroups, coverpoints and bins • Options • Transition coverage • Cross coverage • Procedural sampling and custom sample method • Constructor arguments • Multiple covergroup instances

Arrays and Queues

Describes the data types that SystemVerilog introduces for verification.

Dynamic arrays • Queues • Associative arrays

File I/O

Shows how to read and write files using SystemVerilog.

Opening and closing files • Reading and writing formatted data • Handling errors

The Direct Programming Interface

Shows how to interface between SystemVerilog and C using the Direct Programming Interface (DPI).

Importing and exporting tasks and functions • Passing data between C and SystemVerilog • Changing the function/task name • Calling C++ • DPI flow and simulator switches • Pure and context tasks and functions

Full details below

Looking for team-based training, or other locations?

Complete an enquiry form and a Doulos representative will get back to you.

Contact Enquiry Form