Global training solutions for engineers creating the world's electronics
Menu

Find a Training Course

Welcome attendees of the Verification Futures Conference US 2026

Thanks for taking the time to visit Doulos at this year's conference

This page has brought together a range of Doulos courses and FREE webinars and tutorials for you. Enjoy! 

If you would like to explore training options with Doulos, check out the listing below and then contact your local Doulos team directly, or complete a webform*. 

IP, FPGA and SoC Design and Verification Courses

Self-Paced Training

View full training schedule »

Upcoming EDA KnowHow Webinars

This webinar will discuss the use of Agentic AI to automate your FPGA design flow. Agentic AI will interface with AMD’s Vivado™ IDE to implement design flow automation.

Topics include:

  • Use of an autonomous car analogy to understand an automated design flow

  • Working of Retrieval-Augmented Generation (RAG) based knowledge base to assist Agentic AI

  • Closed loop mechanism to resolve errors in the design flow

  • Use of a Model Context Protocol (MCP) server to interface with a large language model, knowledge base, and Vivado IDE

  • Trade-offs in using cloud-based frontier models or on-perm based local models

  • Creating a deterministic workflow using skills to avoid model hallucinations

  • Pre-built AI agent skills and an example of creating your own custom skill

  • Examples on the use of Agentic AI for block-based design creation, RTL linting, timing closure and insertion of integrated logic analyzer (ILA) probes for design debugging

REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »

Finite State Machines (FSMs) hold internal state information, react when inputs change, and then drive outputs. They are a foundational building block of FPGA or ASIC designs and have many names, including automatons, sequencers, controllers and Petri networks.

This webinar will introduce you to FSMs and elaborate on the practicalities of implementing and verifying them to meet reliability and safety requirements.

Topics include:

  1. Overview of FSM architectures

  2. FSM implementation & synthesis

  3. Causes of FSM failure

  4. Designing & verifying for safety

  5. Verifying safety on silicon

The webinar will also feature some real-world examples from Microchip Technology, using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite, demonstrating how the concepts work in a commercial FPGA device and tool chain. 

REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »

The use of non-determinism with formal is how formal is able to manage large state spaces and still arrive at a quick solution. Non-determinism plays a part in writing our formal constraints, formal targets, and formal abstractions.

This webinar will explain what non-determinism is, how it's used, and show lots of examples so you can take advantage of non-determinism to accelerate the verification of your designs.

It is partnered with Synopsys and all of the examples can be used in VC Formal.

REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »

Check out the latest live webinar schedule »

KnowHow Webinars On-Demand and Tutorials

This webinar will introduce you to the Universal Verification Methodology. The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench.

The webinar will help you to understand:

  • the class hierarchy

  • simulation phases

  • transaction-level communication

  • sequences and sequencers

  • drivers

  • the factory

  • the configuration database

  • objections 

REGISTER & VIEW THIS WEBINAR NOW »

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

  • Wire vs Variable Assignments

  • Static vs Automatic Variables

  • Static vs Automatic Tasks

  • Assignments in Tasks – Pass-by-Copy

  • Assignments in Tasks – Pass-by

  • Reference

  • Enumerations

  • struct and packed struct

  • Equality Operators

  • Equality between vectors

  • SVA Temporal Behavior

 

REGISTER & VIEW THIS WEBINAR NOW »

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary.

This webinar seeks to answer the questions you may not have had answered in the past; shedding light on the mystery of VHDL configurations and showing a practical example of how to apply them, using Synopsys VCS in the Doulos EDA Playground environment.

Topics include:

  • VHDL Entity and Architecture

  • Direct Instantiation

  • Component Declaration and Instantiation

  • VHDL Configuration Declaration

  • Default Binding Rules

  • Hierarchical and Nested Configurations

  • Other Capabilities

  • Compilation Order and Configurations

REGISTER NOW FOR THIS ON-DEMAND WEBINAR

Formal verification is known to work well in areas like control logic, interface protocols, and so on, but it is often dismissed for use on data paths since capacity becomes a significant issue. In particular, packet based protocols have potentially very large state spaces, which can pose a problem for formal. However, in this paper, a step by step process is presented, showing how to decompose a frame of data into simple formal constraints, modeling code, and assertions, which allows formal to fully explore the entire packet state space.

VIEW THIS TUTORIAL ON THE DOULOS WEBSITE NOW »

An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. That is where helper code comes to the rescue. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis. Likewise, formal analysis may need to reduce the complexity of the problem and state space, which helper code can also help. So where are some places to use helper code and when?

This article looks at how helper code can be used to simplify our properties, model formal abstractions, constrain formal inputs, and aid formal analysis.

VIEW THIS ARTICLE ON THE DOULOS WEBSITE NOW »

In this paper, eight common asynchronous scenarios are presented and SVA solutions for checking them. In addition, an alternative approach using a global fast clock is presented as both a portable simulation solution and something that works for both formal verification and emulation. Lastly, incorporating functional coverage into the asynchronous checking is also discussed.

VIEW THIS PAPER ON THE DOULOS WEBSITE NOW »

View all on-demand webinars available »

About Doulos Training

For over 30 years, Doulos has been dedicated to developing the skills, capability and productivity of engineers designing the latest technologies.

The essential choice for independent training to over 5,400 companies spanning 84 countries, Doulos provides scheduled classes and bespoke team training both In-Person and Live Online. The course portfolio includes hardware design and verification languages and methodologies, embedded software, AI and deep learning.

Our business ethos is 'Service through Excellence' which, when combined with our industry-leading KnowHow™, makes Doulos the ideal training partner.

Contact Doulos now »